The present inventive concept relates to voltage control circuits and methods adapted for use in memory devices. More particularly, the inventive concept relates to a circuit in a dynamic random access memory (DRAM) capable of pre-charging a bit line with a voltage corresponding to a half of a power voltage.
In many semiconductor memory devices such as the DRAM, a predetermined pre-charge voltage is applied to a bit line pair, and then data stored in a memory cell connected to the bit line pair is sensed on the basis of a voltage variation apparent on the bit line pair in response to an applied sensing enable signal.
It is typical for the DRAM to pre-charge the bit line pair to one half of a power voltage using a conventionally understood pull-up/pull-down operation. By a pulling-up/pulling down the voltage applied to a transistor of a conventional pre-charge circuit, the bit line pair may be pre-charged to a voltage equal to one half a power voltage.
However, in many conventional pre-charge circuits there is a risk that a DC current path may be unintentionally formed between the power voltage and ground during the pull-up/pull-down operation. Such an occurrence may be caused by the pull-up/pull down transistors being turned ON simultaneously due to a mismatch between the transistors. The resulting circuit condition is referred to as a dead zone wherein all of the pull-up/pull-down transistors are open. This dead zone condition may be formed with about tens of milli-volts (mV) of amplitude, and the conventional pre-charge circuit may not pre-charge the power voltage to ½ when operating in the dead zone.
The data sensing problems that result from inadequate dead zone pre-charging have become recently more acute as the unit element size and corresponding operating voltages of contemporary DRAMs have been reduced. That is, even a reduction in the range of tens of milli-volts in the dead zone will adversely impact DRAM sensing margins.